1. Technical Field
The present disclosure relates to a smart card and a method of testing the smart card, and more particularly, to a smart card employing a BIST (built-in self test) scheme for increasing the number of smart cards that can be tested in parallel, and a method of testing the smart card.
2. Discussion of the Related Art
Testing a smart card may include a first step of testing an interface between the smart card and a host, a second step of testing an operation of a non-volatile memory, and a third step of testing operations of peripheral devices. For example, the peripheral devices may include a peripheral circuit, a volatile memory, a ROM, etc.
The second testing step may require more processing time than either of the first or third steps, because the capacity of the non-volatile memory greatly increases with high integration due to a segmentation of the non-volatile memory process.
Accordingly, it can be beneficial to reduce the testing time of the second testing step. Test performance can be improved by using a multi-parallel test to test a plurality of smart cards together in a tester.
However, as the capacity of the non-volatile memory increases, the time required to test the non-volatile memory greatly increases. Efforts have also been made to improve testing performance by increasing the number of channels of a tester. However, there is a limit to the number of channels a tester can be increased.
FIG. 1 is a block diagram of a conventional smart card 100. Referring to FIG. 1, the smart card 100 includes a bus 110, a plurality of pads 120, a peripheral circuit 130, a volatile memory such as RAM 140, a ROM 150, a non-volatile memory (NVM) 160, and a CPU 170. The smart card 100 receives testing signals (e.g., a ground voltage GND, a power supply voltage VDD, a reset signal RESET a clock signal CLK, a testing signal TEST, and a data signal DATA) input to the corresponding pads 120, and starts a testing operation.
When testing of the smart card 100 starts, the smart card 100 tests the non-volatile memory 160 in response to the received testing signals (e.g., the ground voltage GND, the power supply voltage VDD, the reset signal RESET, the clock signal CLK, the testing signal TEST, and the data signal DATA) and outputs the result(s) of the testing to a tester via an input/output (I/O) pad which is one of the pads 120.
A tester for testing the smart card 100 may control the testing signals by allocating as many channels as the number of testing signals which are required when testing the smart card 100. For example, the tester may control the testing signals by allocating at least 5-6 channels in testing the single smart card 100. As described above, there is a limit to increasing the number of channels in the tester, and thus the number of devices to practice the multi-parallel test in the smart card 100 is limited.
Thus, there is a need for a method of increasing the number of smart cards that can be tested according to the multi-parallel test that decreases the number of channels required by the tester.